Design and Analysis of Adders Using Pass Transistor Logic for Multipliers

Multipliers and adders are very important elements in digital electronics they have applications in signal processing, image processing, cryptography, and communication systems. All such applications require that the calculation be fast with a low power consumption and a low area, which calls for optimum designing of these elements in VLSI. Half and full adders are the basic components of this multiplier. This project specializes in designing and enforcing a four-bit Multipliers by the use of pass transistor logic to decorate the overall performance of half and full adders. Pass transistor logic further boosts performance through reducing switching and leakage currents, making it a surprisingly suitable preference for transportable and embedded systems. This technique reduces the overall transistor count number, resulting in a more compact and cost-powerful design. moreover, it ensures scalability, demonstrating its relevance across advanced generation nodes like 90 nm and 45nm CMOS processes. In this project, half and full adders are optimized in a 4-bit Multiplier with significant improvements over digital circuit design. The results demonstrate dramatic improvements in delay, power consumption, and transistor count relative to traditional designs. setting a firm foundation of low-energy high-performance arithmetic units. The main motivation behind this work is the increasing demand for efficient digital systems that can compute complex arithmetic operations within a power constrained environment. Modern applications, such as AI accelerators, embedded systems, and high-speed processors, need arithmetic cores that are operated at high speeds but with low power and area on silicon. Those old designs of multipliers and adders are functional but, in most cases, do not work under the above-mentioned stringent requirements due to huge delay, increased power dissipation, and increased count of transistors. With advancing technology scaling, the requirement for efficient design increases since devices are very compact, faster, and densely integrated.

LITERATURE SURVEY

METHODOLOGY

1. Pass Transistor Logic For several decades, designing low-power adders and multipliers has remained a major research area of interest due to the rapidly increasing demand for energy-efficient and high-performance digital circuits in modern VLSI systems. So far, traditional approaches focus on CMOS logic in designing. CMOS logic is highly robust and possesses noise immunity, thus gaining popularity in the field of digital circuits. However, it has some disadvantages, especially related to power area optimization and speed. These are very significant in advanced technology nodes like 90 nm, where transistor scaling introduces new challenges like leakage power as well as increased circuit density.

Fig 1: NMOS PTL Technique

The basic pass transistor logic configuration, wherein the transistor is used as a switch to transfer the input signal from the input, Vin, to the output, Vout. The switching action of the transistor is controlled by a control signal, which may put the transistor in the ON or OFF state. When the signal is high (logic 1), the transistor conducts that enables the input voltage (Vin) to pass along to the output (Vout). On the other hand, when the signal is low or logic 0, the transistor will turn off, thus ensuring isolation of the input with the output. This simple design for PTL is widely used due to its lower transistor count that contributes to reduced power dissipation and compact implementation, thus contributing to energy-efficient systems. Voltage levels and signal loss must be taken into careful consideration in cascading circuits. By using this PTL logic first we implement basic gates and then we implement this basic gates to adders.

2. PTL Based and Gate