Design and Analysis of Adders Using Pass Transistor Logic for Multipliers

Multipliers and adders are very important elements in digital electronics they have applications in signal processing, image processing, cryptography, and communication systems. All such applications require that the calculation be fast with a low power consumption and a low area, which calls for optimum designing of these elements in VLSI. Half and full adders are the basic components of this multiplier. This project specializes in designing and enforcing a four-bit Multipliers by the use of pass transistor logic to decorate the overall performance of half and full adders. Pass transistor logic further boosts performance through reducing switching and leakage currents, making it a surprisingly suitable preference for transportable and embedded systems. This technique reduces the overall transistor count number, resulting in a more compact and cost-powerful design. moreover, it ensures scalability, demonstrating its relevance across advanced generation nodes like 90 nm and 45nm CMOS processes. In this project, half and full adders are optimized in a 4-bit Multiplier with significant improvements over digital circuit design. The results demonstrate dramatic improvements in delay, power consumption, and transistor count relative to traditional designs. setting a firm foundation of low-energy high-performance arithmetic units. The main motivation behind this work is the increasing demand for efficient digital systems that can compute complex arithmetic operations within a power constrained environment. Modern applications, such as AI accelerators, embedded systems, and high-speed processors, need arithmetic cores that are operated at high speeds but with low power and area on silicon. Those old designs of multipliers and adders are functional but, in most cases, do not work under the above-mentioned stringent requirements due to huge delay, increased power dissipation, and increased count of transistors. With advancing technology scaling, the requirement for efficient design increases since devices are very compact, faster, and densely integrated.

LITERATURE SURVEY

METHODOLOGY

1. Pass Transistor Logic For several decades, designing low-power adders and multipliers has remained a major research area of interest due to the rapidly increasing demand for energy-efficient and high-performance digital circuits in modern VLSI systems. So far, traditional approaches focus on CMOS logic in designing. CMOS logic is highly robust and possesses noise immunity, thus gaining popularity in the field of digital circuits. However, it has some disadvantages, especially related to power area optimization and speed. These are very significant in advanced technology nodes like 90 nm, where transistor scaling introduces new challenges like leakage power as well as increased circuit density.

Fig 1: NMOS PTL Technique

The basic pass transistor logic configuration, wherein the transistor is used as a switch to transfer the input signal from the input, Vin, to the output, Vout. The switching action of the transistor is controlled by a control signal, which may put the transistor in the ON or OFF state. When the signal is high (logic 1), the transistor conducts that enables the input voltage (Vin) to pass along to the output (Vout). On the other hand, when the signal is low or logic 0, the transistor will turn off, thus ensuring isolation of the input with the output. This simple design for PTL is widely used due to its lower transistor count that contributes to reduced power dissipation and compact implementation, thus contributing to energy-efficient systems. Voltage levels and signal loss must be taken into careful consideration in cascading circuits. By using this PTL logic first we implement basic gates and then we implement this basic gates to adders.

2. PTL Based and Gate

Fig 2: Circuit diagram of AND Logic

Basically, PTL is based on twin transistor network. So, as shown above the PTL is implemented for the AND gate using Nmos.

3. PTL Based or Gate

Fig 3: Circuit diagram of OR Logic

as shown above the PTL is implemented for the OR gate using Nmos.

4. PTL Based X-Or Gate

Fig 4: Circuit diagram of XOR Logic

As shown above the PTL is implemented for the X-OR gate using Nmos

5. PTL Based X-Nor Gate

Fig 5: Circuit diagram of XNOR Logic

Table 4: Truth Table for Xnor Logic

As shown above the PTL is implemented for the X-NOR gate using Nmos.

1. Design Techniques

The proposed half adders and full adder is to create 4x4-bit multiplier, which both in terms of area and power efficiency. Different structures can be used to develop multipliers

1. Design of Half Adder

In this proposed Half Adder, we use PTL based AND and X-OR gates. With comparison to previous work, the novelty present in the proposed work makes the circuit as low power and area reduction.

Table 5: Truth Table for Half Adder

Fig 6: Circuit diagram of Half Adder

Fig 7: Half Adder using PTL on Cadence Virtuoso

The novelty shown in the fig, makes the combination to provide full swing half adder, a double inverter is provided to perform both AND and XOR logic respectively. The design that provided as a novel is to reduce static power consumption.

2. Design of Full Adder

In this proposed Full Adder, we use PTL based AND, OR, XNOR and X-OR gates. With comparison to previous work, the novelty present in the proposed work makes the circuit as low power and area reduction.

Table 6: Truth Table for Full Adder

Fig 8: Circuit diagram of Full Adder

Fig 9: Full Adder using PTL on Cadence Virtuoso

The novelty shown in the fig, makes the combination to provide full swing half adder, a three inverter is provided to perform AND, OR, XNOR and XOR logic respectively. The design that provided as a novel is to reduce static power consumption.

2. Design of Multipliers C.S. Wallace developed the Wallace tree multiplier method in 1964 as a technique that enables fast multiplication with the least possible delay. This method While it demands large computational resources, it excels in delay minimization, which scales proportionally with the logarithm of the word length. The Wallace tree Methodology is generally preferred in situations where speed is more important than area efficiency. The Wallace tree multiplier has three distinct phases of operation, as illustrated in Figure 2. First it produces partial products from the binary multiplication of input bits

1. Array Multilier

multiplier structure is presented in Fig. to demonstrate the usefulness of the suggested AND, half adder, and full adder.

Fig 10: Circuit Diagram of Array Multiplier

Fig 11: Multiplier using proposed logic on cadence virtuoso

2. Wallace Tree Multiplier

Multiplier structure is presented in Fig. to demonstrate the usefulness of the suggested AND, half adder, and full adder.

Fig 10: Circuit Diagram of Wallace Tree Multiplier

Fig 13: Multiplier using proposed logic on cadence virtuoso

RESULT AND ANALYSIS

The circuits that are presented in this multiplier structure are designed for 90nm and 45nm technology at a supply voltage of 1.2V. Cadence Virtuoso software is used to simulate all of the circuits in the multiplier. TABLE 7,8,9,10 are the comparisons for half adder, full adder, and multipliers, respectively, with existing logic. Fig.14., Fig.15., Fig.16., Fig.17. are proposed Half adder, Full adder and multipliers respectively.

1. Transient Analysis of Half Adder

Fig 14: waveform of proposed half adder

2. Transient Analysis of Full Adder

Fig 15: waveform of proposed half adder

3. Transient Analysis of Array Multiplier

Fig 16: waveform of proposed half adder

4. Transient Analysis of Wallace Tree Multiplier

Fig 17: waveform of proposed half adder

Table 7: Comparison of Half Adder

Table 8: Comparison of Full Adder

                                     Table 9: Comparison of Wallace Tree Multiplier

Table 10: Comparison of Array Multiplier